This invention relates to the field of frequency synthesis. More particularly, this invention relates to phase-locked loop frequency synthesis in which a phase-locked loop is augmented to provide frequency resolution greater than that attainable with a conventional phase-locked loop circuit.
As is known in the art, the term "frequency synthesis" encompasses various methods and apparatus wherein a frequency conversion process is utilized to translate the signal frequency of one or more reference signals to a generally large number of output signal frequencies that are relatively stable in frequency and relatively pure in spectral content, each of which output frequencies can be individually selected as the frequency of the synthesizer output signal. As is further known, frequency synthesis is utilized in a wide range of applications in which a number of stable, spectrally pure signal frequencies are required. For example, to eliminate the large number of crystal controlled oscillators that would otherwise be required, frequency synthesis is often employed in channelized communication systems, especially those communication systems that employ frequency-hopping techniques, test and instrumentation systems, and frequency-agile radar systems.
Three basic frequency synthesis techniques have become known within the art and are commonly identified as direct frequency synthesis, indirect frequency synthesis and digital frequency synthesis. In apparatus employing direct frequency synthesis, the output frequencies are obtained directly from the frequency of one or more reference signals by the operations of mixing, filtering, frequency multiplication and frequency division. Indirect synthesizers derive the output frequency from a secondary oscillator that is either phase-locked or frequency-locked to the frequency of a reference signal. Hence, such indirect frequency synthesizers often employ conventional phase-locked loop circuits. In contrast, digital synthesis is a sampled data technique in which a reference signal determines an invariant sampling interval and real-time digital computation is employed to calculate signal amplitudes, which when filtered, result in an analog signal of the desired frequency.
Each of the basic frequency synthesis techniques exhibits performance characteristics that often make a particular type of frequency synthesizer preferable in a particular design situation. For example, circuits which employ only direct synthesis techniques are not especially well-suited for applications requiring the synthesis of a signal over a relatively wide frequency range, e.g., one or more octaves, since the output signals of such a circuit inherently exhibit a relatively low percentage bandwidth. Further, circuits employing direct frequency synthesis are generally complex, requiring a large number of circuit stages including a relatively large number of multiple pole filter arrangements.
Although various techniques, such as down conversion or heterodyning of the signal supplied by a direct synthesizer, have been developed to effectively expand the bandwidth of the output signal, these techniques are not entirely satisfactory. In particular, in such a heterodyning or beat-frequency system, the direct synthesis stages must operate at frequencies substantially higher than the final output frequency. This high frequency operation complicates the design of appropriate circuitry, often leads to substantial power consumption, generally results in a circuit of relatively high cost, and often increases the amount of noise or spurious signal components present in the synthesized output signal.
On the other hand, indirect synthesis techniques which employ phase-locked loop circuits have a relatively low parts count and are inherently capable of supplying a synthesized signal over a relatively wide frequency range. Because of this, a circuit arrangement commonly called a programmable divide-by-N phase-locked loop is often advantageous in situations where output bandwidth is of prime consideration.
Such a programmable divide-by-N phase-locked loop is essentially a feedback or simple servo system in which an error signal that is proportional to the phase difference between a feedback signal and a reference signal is generated within a phase detector circuit. This error signal is low-pass filtered and utilized to control the frequency of a voltage controlled oscillator circuit (VCO) which supplies the system output signal. In this arrangement, frequency control is effected by a programmable frequency divider circuit which is connected for receiving the output signal of the VCO and supplies the feedback signal to the phase detector. In particular, the programmable divider reduces the frequency of the feedback signal by a selectable factor N and, since the loop will synchronize or lock when the phase of the feedback signal is substantially identical to the phase of the reference signal, causes the VCO to supply a signal at the frequency Nf.sub.r where f.sub.r is the frequency of the reference signal.
Since N is an integer in conventional programmable dividers, the basic divide-by-N phase-locked loop is limited to a frequency resolution equal to the reference frequency f.sub.r. Further, since the time required to switch from one output frequency to another is inversely proportional to f.sub.r and noise performance is generally degraded as f.sub.r is decreased, oftentimes a basic programmable divide-by-N phase-locked loop cannot simultaneously achieve the desired output bandwidth and frequency resolution along with a desired switching speed and the desired level of noise suppression. To overcome this drawback, several design approaches that are generally categorized as augmented phase-locked loops have been developed. For example, techniques which permit the programmable divisor N to take on noninteger values and multiple loop arrangements have been proposed.
Although prior art systems for augmenting a programmable divide-by-N phase-locked loop to thereby provide relatively wide bandwidth and relatively high frequency resolution have proven somewhat satisfactory under certain design situations, each of these systems generally suffers from one or more drawbacks. For example, often such arrangements are extremely complex in structure, hence increasing circuit cost and often decreasing circuit reliability. Further, such synthesis systems often require rather complex programming or switching circuits in order to establish the output frequency at a desired value.
Accordingly, it is an object of this invention to provide an augmented programmable divide-by-N phase-locked loop having a relatively high frequency resolution and a relatively wide output bandwidth, e.g., one or more octaves.
It is another object of this invention to provide an augmented phase-locked loop synthesizer circuit having a relatively low parts count, such circuit being capable of synthesizing an output signal over at least an octave wide frequency range with relatively high frequency resolution.
It is yet another object of this invention to provide an augmented phase-locked loop frequency synthesizer having a relatively wide output frequency range and relatively high frequency resolution in which a desired output frequency can be initiated by simple programming signals.